1. Field of the Invention
The present invention relates to an internal voltage generator for a semiconductor memory device, and in particular to an internal voltage generator for improving an initial power-up operation property of a semiconductor memory device under a low external power voltage.
2. Description of the Background Art
In the conventional art, when a low external power voltage is supplied to a semiconductor memory device, generation of an internal voltage in an initial power-up operation is delayed, and thus operation of the whole system is also delayed. This results in a mis-operation of the system.
Referring to FIG. 1, a conventional internal voltage generator includes: a control signal generator 1 for generating a control signal C0 by using a general external power voltage VDD-1; and an internal voltage generating circuit 2 for generating internal voltages Vref-1, Vint-1 and Vint2-1 in response to the control signal C0.
The disadvantages of the conventional internal voltage generator will be explained in detail with reference to FIGS. 2 and 3.
FIG. 2 is a timing diagram of the initial power-up operation in a state where the general external power voltage is supplied to the semiconductor memory device. FIG. 3 is a timing diagram of the initial power-up operation in a state where the low external power voltage is supplied to the semiconductor memory device.
In FIGS. 2 and 3, VDD-1 denotes the general external power voltage, and VDD denotes the low external power voltage. Vref-1 denotes the reference voltage for internal power generated by VDD-1, and Vref denotes a reference voltage for internal power generated by VDD. Vint-1 denotes the first internal voltage generated according to Vref-1, and Vint denotes a first internal voltage generated according to Vref. Vint2-1 denotes a second internal voltage generated by Vint-1, and Vint2 denotes a second internal voltage generated by Vint2. A represents the time point when the first internal voltages Vint and Vin-1 reach an aimed voltage level. B represents the time point when the second internal voltages Vint2 and Vint2-1 reach an aimed voltage level.
As illustrated in FIG. 3, when the low external power voltage is supplied to the semiconductor memory device, the reference voltage Vref for internal power is delayed due to the low voltage in the initial power-up operation, thereby delaying the generation of the first internal voltage Vint and the second internal voltage Vint2 (t1 denotes a time when the external power voltage reaches the aimed voltage level, and t2 denotes a specification value of the second internal voltage Vint2 which is finally generated) . As a result, the generation time of the second internal power voltage Vint2 exceeds the aimed voltage reaching time t2.
Accordingly, it is an object of the present invention to prevent generation of an internal voltage from being delayed in an initial power-up operation, by generating a ramp-up voltage higher than a low external power voltage, if the low external power voltage is supplied to a semiconductor memory device.
In order to achieve the above-described object of the invention, there is provided a first embodiment of an internal voltage generator for a semiconductor memory device. The internal voltage generator comprises a control signal generator, a ramp-up voltage generator, a switching circuit, and an internal voltage generating circuit. The control signal generator generates first and second control signals for controlling generation of a ramp-up voltage. The ramp-up voltage generator generates a ramp-up voltage higher than a low external power voltage in response to the first and second control signals. The switching circuit selectively transmits either the ramp-up voltage or the low external power voltage in response to the second control signal. The internal voltage generating circuit selectively receives either the ramp-up voltage or the low external power voltage from the switching circuit, and generates a plurality of internal voltages.
In addition, there is provided a second embodiment of an internal voltage generator for a semiconductor memory device. The internal voltage generator comprises first to fourth control signal generators, first and second ramp-up voltage generators, first and second switching circuits, and an internal voltage generating circuit. The first control signal generator generates first and second control signals for controlling generation of a first ramp-up voltage. The second control signal generator generates a third control signal for controlling generation of a second ramp-up voltage and a high voltage. The third control signal generator receives and synthesizes the second control signal and the third control signal, and generates a fourth control signal for controlling generation of the second ramp-up voltage and the high voltage. The first ramp-up voltage generator generates the first ramp-up voltage higher than the low external power voltage in response to the first control signal. The second ramp-up voltage generator generates the second ramp-up voltage and the high voltage higher than the low external power voltage in response to the second control signal and the fourth control signal. The first switching circuit is switched according to the second control signal, and for selectively transmitting either the second ramp-up voltage or the high voltage. The second switching circuit is switched according to the second control signal, and for selectively transmitting either the first and second ramp-up voltages or the low external power voltage. The internal voltage generating circuit selectively receives either the first and second ramp-up voltages or the low external power voltage from the second switching circuit, and generates a plurality of internal voltages. The fourth control signal generator receives one of the plurality of internal voltages, and generates a fifth control signal for deciding a level of the second control signal.